Self-healing Ability of Sequential Circuits

1. Introduction Two different ideologies can be considered for handling an error detected in a circuit concurrently with its functioning. The first ideology is based on the immediate marking of the circuit as erroneous when an error is detected. An alternative ideology concentrates on increasing the survivability of the circuit, which means, "to give a chance" to the circuit to continue to work during a number of clock cycles after the error detection, and marking it as erroneous only after a steady error is indicated. Sometimes these several clock cycles are sufficient for the recovery of a transient fault and for returning the circuit to its proper functioning. The first of the above-mentioned ideologies has an advantage in the low fault latency. The second one offers a way for circuits to survive in cases of transient faults. In the present paper we investigate architectures that enable circuits to survive without introducing any additional overhead. We deal with microcontrollers described by Finite State Machines (FSMs) and implemented as Synchronous Sequential Circuits (SSCs). We use the onset realization of output and next state functions. Furthermore, we deal with implementations where both the next state and output equations are unate [1] in state variables and binate in primary input variables. SSCs that are implemented according to such a scheme we call state monotonic SSCs. In most cases using these implementations results in a considerable reduction in overhead [2,3]. Furthermore, and that is substantial in the present work, such SSCs can function properly with the presence of a fault and even recover from the fault. This property is called self-healing. The proposed synthesis technique implements self-healing SSC and minimizes the required overhead. We investigate the techniques from the point of overheads, assuming that the resulting on-line checking controller will be implemented by a FPGA.